(1) Technical Field
This invention relates to electronic circuits, and more particularly to gate voltage generation circuits for field effect transistor switch devices in radio frequency circuits.
(2) Background
Field effect transistors (FETs) are common circuit elements in modern electronic systems, and comprise a semiconductor body having a source, a drain, and a control gate. FETs may be fabricated in a number of integrated circuit (IC) technologies, such as the well-known standard bulk silicon, silicon-on-insulator (SOI) (including silicon-on-sapphire, or “SOS”), GaAs pHEMT, and MESFET IC technologies. One common use of field effect transistors (FETs) is as signal switching devices in radio frequency (RF) circuits.
Not all FETs have the same electrical characteristics, which often vary by fabrication process. For example, SOI-based FETs for switching RF signals typically require well-tuned gate drive voltages for optimal results. Typically, larger gate voltages allow for better RF characteristics (e.g., linearity, power handling capability), but can also lead to higher body leakage and to increased device stress, which can limit lifetime. Thus, in setting the gate voltage of an RF signal switching FET, a compromise must be made between performance, reliability, and power consumption required to overcome body leakage.
Focusing now on gate voltages for FET switch devices for RF applications that are fabricated in an SOI technology (including SOS), and in fabrication technologies having similar characteristics, in the oldest generations of such FETs, it was common to use the positive IC voltage supply, +VDD, to turn a FET “ON”, and the negative IC voltage supply, −VDD, to turn the FET “OFF”. In a next generation, it became common to use the positive IC voltage supply, +VDD, to turn a FET “ON”, but to use a negative voltage other than −VDD to turn the FET “OFF”. Currently it is common to use a positive voltage other than +VDD to turn a FET “ON”, and to use a negative voltage other than −VDD to turn the FET “OFF”. Modern RF ICs fabricated in an SOI technology typically use precision reference voltages to set fixed positive and negative FET gate drive voltages independent of the IC voltage supply, VDD, and its inverse, −VDD. (Note that in some types of FETs, such as enhancement mode FETs, the OFF state gate voltage may be zero volts; accordingly, more generally, as used herein, “positive voltage” or “positive gate voltage” means the voltage level required to turn a FET “ON”, and “negative voltage” or “negative gate voltage” means the voltage level required to turn a FET “OFF”).
In some RF circuit applications utilizing such FET switch devices, there may be high and low performance channels. One example is a radio transmit/receive circuit with FET switch devices defining signal paths—the transmit signal path generally requires a low insertion loss (IL) and high voltage standoff capability, while the receive signal path has less stringent IL and voltage standoff requirements. Typically, the FET gate drive voltage which creates the best RF performance in a particular RF signal path (e.g., the transmit signal path) is chosen for all of such FETs, which exposes the FETs in other signal paths to non-optimal or more stressful conditions due to a higher applied gate drive voltage.
In a number of cases (such as in factory characterization testing or component qualification testing), in order to evaluate the lifetime of an RF circuit with PET switch devices, it is desirable to overdrive the FET gate voltage to stress the FET device. Increased device stress reduces lifetime, and thus shortens testing time. However, this has not been possible with fixed FET gate drive voltages.
Accordingly, there is a need to be able to select among multiple different positive and/or multiple different negative FET gate drive voltages for FETs in which well-tuned gate drive voltages are needed or desirable for optimal results. The present invention addresses this need.